Embedded capacitor structure and the forming method thereof

ABSTRACT

A method for forming an embedded capacitor structure is provided. Firstly, a first dielectric layer having a trench therein on a substrate is provided. A capacitor structure is formed on the bottom surface of the trench. The capacitor structure includes a first metal layer, a capacitance-insulating layer and a second metal layer and the portion surface of the first metal layer on the bottom surface of the trench is exposed. A cap layer is formed on the top surface and the inner surface of the trench and on the capacitor structure. A second dielectric layer is formed on the cap layer. The portion of second dielectric layer and the portion of the cap layer are removed to form a plurality of contact windows therein, and the portion surface of the first metal layer and the portion surface of the second metal layer are exposed by the plurality of contact windows.

FIELD OF THE INVENTION

The present invention relates to an embedded capacitor structure, andmore particularly to a process for forming an embedded capacitorstructure using only one silicon nitride deposition process.

BACKGROUND OF THE INVENTION

The purpose of the integrated circuit is to integrate the various typesof electronic components to the semiconductor substrate byminiaturization. Thus, the capacitor must be completed in the integratedcircuit in demand. However, the conventional process of the embeddedcapacitor is too complicated, for example, it need to be repeated atdifferent stages of silicon nitride deposition process in order tocomplete the structure of the conventional capacitor, so that the costof the manufacturing process is higher. Thus, the purpose of the presentinvention is to improve the lack of the conventional embedded capacitorstructure.

SUMMARY OF THE INVENTION

The object of the present invention is to provide a method for formingan embedded capacitor structure, such that the number of the siliconnitride layer deposition processes can be diminished to reduce themanufacturing cost. In accordance with the object, the present inventionprovides a method for forming an embedded capacitor structure. Firstly,a first dielectric layer having a trench therein on a substrate isprovided. A capacitor structure is formed on the bottom surface of thetrench. The capacitor structure includes a first metal layer, acapacitance-insulating layer and a second metal layer and the portionsurface of the first metal layer on the bottom surface of the trench isexposed. A cap layer is formed on the top surface and the inner surfaceof the trench and on the capacitor structure. A second dielectric layeris formed on the cap layer. The portion of second dielectric layer andthe portion of the cap layer are removed to form a plurality of contactwindows therein, and the portion surface of the first metal layer andthe portion surface of the second metal layer are exposed by theplurality of contact windows.

In an embodiment, the material of the first dielectric layer is made ofsilicon dioxide or Fluorinated Silica Glass (FSG).

In an embodiment, the capacitor structure further includes the steps offorming a first metal layer on the top surface, the inner surface andthe bottom surface of the trench, forming the capacitor layer on asurface of the first metal layer, forming the second metal layer on asurface of the capacitance-insulating layer, forming a bottomanti-reflection coating layer on the second metal layer and to fill withthe trench, forming a photoresist layer with the capacitor structurepattern over the bottom anti-reflection coating layer; and etching toremove the bottom anti-reflection coating layer, the portion of thesecond metal layer, the portion of the capacitance-insulating layer andthe portion of the first metal layer to form the capacitor structure onthe bottom surface of the trench, and to expose the portion surface ofthe first metal layer and the portion surface of the second metal layeron the bottom surface of the trench.

In an embodiment, the material of the bottom anti-reflection coatinglayer is made of silicon nitride (SiN), silicon dioxide (SiO₂) orsilicon oxynitride (SiON).

In an embodiment, the first metal layer on the bottom surface of thetrench is contacted with the portion inner surface of the trench.

In an embodiment, the first metal layer with a thickness is in a rangearound 1000 angstroms.

In an embodiment, the capacitance-insulating layer with a thickness isin a range from 300 angstroms to 600 angstroms.

In an embodiment, the second metal layer with a thickness is in a rangefrom 600 angstroms to 1000 angstroms.

In an embodiment, the cap layer with a thickness is in a range from 350angstroms to 700 angstroms.

In an embodiment, the contact window is a single damascene structure ora dual damascene structure.

In an embodiment, the method for forming an embedded structure furtherincludes the step of forming a metal layer in the plurality of contactwindows to form a plurality of conductive connecting structures.

According to the method for forming the embedded capacitor structure,the present invention provides an embedded capacitor structure. Theembedded capacitor structure includes a first dielectric layer on thesubstrate and a trench in the first dielectric layer, a capacitorstructure on the bottom surface of the trench. The capacitor structureincludes a first metal layer on the bottom surface of the trench, acapacitance-insulating layer on the first metal layer and a second metallayer on the capacitance-insulating layer. The capacitance-insulatinglayer and the second metal layer exposed the portion surface of thefirst metal layer and there is a distance between thecapacitance-insulating layer and the second metal layer and the innersurface of the trench. A cap layer is formed on the inner surface of thetrench and covered on the capacitance-insulating layer. A second metallayer is formed on the cap layer. A plurality of conductive connectingstructures is formed within the second dielectric layer and the caplayer, wherein the portion of the plurality of conductive connectingstructures is electrically connected with the portion exposed surface ofthe first metal layer and another portion of the plurality of conductiveconnecting structures is electrically connected with the portion exposedsurface of the second metal layer.

In an embodiment, the material of first dielectric layer is made ofsilicon dioxide or Fluorinated Silica Glass (FSG).

In an embodiment, the portion exposed surface of the first metal layeris adjacent one side or two sides of the inner surface of the trench.

In an embodiment, the distance between the capacitance-insulating layerand the second metal layer and the inner surface of the trench is inrange from 0.9 um to 1 um.

In an embodiment, the material of capacitance-insulating layer is madeof silicon dioxide, silicon nitride, tantalum pentoxide (Ta₂O₅),aluminum oxide or other insulating material.

In an embodiment, the material of cap layer is made of silicon nitride(SiN) or silicon carbide (SiC).

In an embodiment, the material of second dielectric layer is made ofTantalum pentoxide (Ta₂O₅) or aluminum oxide (Al₂O₃).

In an embodiment, the conductive connecting structure is a singledamascene structure or a dual damascene structure.

BRIEF DESCRIPTION OF THE DRAWINGS

The above objects and advantages of the present invention will becomemore readily apparent to those ordinarily skilled in the art afterreviewing the following detailed description and accompanying drawings,in which:

FIG. 1 schematically illustrates a dielectric layer having a trenchtherein on the substrate according to an embodiment of the presentinvention;

FIG. 2 schematically illustrates a first metal layer, acapacitance-insulating layer, a second metal layer and a bottomanti-reflection coating layer formed on the trench;

FIG. 3 schematically illustrates a capacitor structure formed on thebottom surface of the trench;

FIG. 4 schematically illustrates cap layer and a second dielectric layerformed on the inner surface of the trench and on the capacitorstructure;

FIG. 5 schematically illustrates a contact window formed in the trenchand on the capacitor structure; and

FIG. 6 schematically illustrates a metal layer formed in the contactwindow to form a conductive connecting structure in the trench and onthe capacitor structure.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The present invention will now be described more specifically withreference to the following embodiments. It is to be noted that thefollowing descriptions of preferred embodiments of this invention arepresented herein for purpose of illustration and description only. It isnot intended to be exhaustive or to be limited to the precise formdisclosed.

FIG. 1 to FIG. 6 schematically illustrates the process flow for formingthe embedded capacitor structure according to the present invention.Firstly, a first dielectric layer 12 is formed on the substrate 10.Then, a photoresist layer with a trench pattern (not shown) is formedover the first dielectric layer 12 by the optical lithography process.Next, an etching process is performed to remove the portion of the firstdielectric layer 12 to form a trench 122 in the first dielectric layer12 on the substrate 10. In this embodiment, the substrate 10 is siliconsubstrate, and the material of the first dielectric layer is made ofsilicon dioxide (SiO₂) or Fluorinated Silica Glass (FSG).

Please refers to FIG. 2. In FIG. 2, a first metal layer 22 is formed ona top surface, an inner surface and a bottom surface of the trench 122.Then, a capacitance-insulating layer 24 is formed on a surface of thefirst metal layer 22, and a second metal layer 26 is formed on a surfaceof the capacitance-insulating layer 24. In this embodiment, the materialof the first metal layer 22 and the second metal layer 26 is made oftungsten (W), titanium (Ti), tungsten titanium (TiW), tantalum (Ta),tantalum nitride (TaN), aluminum (Al) copper (Cu), or the combinationthereof. The first metal layer 22 and the second metal layer 26 areformed by chemical vapor deposition (CVD), physical vapor deposition(PVD), evaporation, plating or the combination thereof. The first metallayer 22 with a thickness is in around 1000 angstroms (depends on therequirement of the application on the bottom surface of the trench 122,and the second metal layer 26 with a thickness is in a range from 600angstroms to 1000 angstroms (or depends on the requirement of theapplication) on the capacitance-insulating layer 24. The material ofcapacitance-insulating layer 24 is made of silicon dioxide (SiO₂),silicon nitride (SiN), Tantalum pentoxide (Ta₂O₅), aluminum oxide, orother insulating material. The capacitance-insulating layer is formed byCVD, PVD or other deposition method. The capacitance-insulating layer 24with a thickness is in a range from 300 angstroms to 600 angstroms (ordepends on the requirement of the application) between the first metallayer 22 and the second metal layer 26.

Please also refer to FIG. 2, in order to prevent the standing waveeffect and notching effect of the photoresist layer to cause theinterference effect for the incident light and reflection layer tointroduce the inaccuracy of the lithography pattern transferring whenthe lithography process is performed, a bottom anti-reflection coatinglayer (BARC) 30 is formed on the second metal layer 26 and to fill withthe trench 122. In this embodiment, the BARC layer 30 is formed by CVDor other deposition method. the material of the BARC layer 30 is made ofsilicon nitride (SiN), silicon dioxide (SiO₂), or silicon oxynitride(SiON).

Next, a photoresist layer with a capacitor structure pattern (not shown)is formed over the BARC layer 30. An etching process is performed toremove the portion BARC layer 30, the portion of second metal layer 26,the portion of capacitance-insulating layer 24 and the portion of thefirst metal layer 22. Then, the remaining BARC layer 30 is fullyremoved, such that the first metal layer 222, the capacitance-insulatinglayer 242 and the second metal layer 262 are remained on the bottomsurface of the trench 122. The portion surface of the first metal layer222 is exposed and the first metal layer 222 is contacted with the innersurface of the trench 122 as shown in FIG. 3. In this embodiment, theportion of exposed surface of the first metal layer 222 is adjacent oneside or two sides of the inner surface of the trench 122. In addition,the width for the portion of the exposed surface of the first metallayer 222 is a distance between the capacitance-insulating layer 242 andthe second metal layer 262 and the inner surface of the trench 122, thedistance is in range from 0.9 um to 1 um. Moreover, the first metallayer 222, the capacitance-insulating layer 242 and the second metallayer 262 is constructed a metal/insulator/metal capacitor structure 20.

Please refer to FIG. 4. In FIG. 4, a cap layer 40 is formed on the topsurface and the inner surface of the trench (not shown) and on thecapacitor structure 20. The cap layer 40 is used as an etching stoplayer for forming the contact window (not shown) in subsequent process.In this embodiment, the cap layer 40 is formed by CVD and the thicknessis in a range 350 angstroms to 700 angstroms (or depends on the processcapability). The material of cap layer 40 is made of silicon nitride(SiN) or Silicon Carbide (SiC). Next, please also refer to FIG. 4, asecond dielectric layer 50 is formed on the cap layer 40 and to fillwith the trench.

A chemical mechanical polishing process is performed to remove theunnecessary second dielectric layer 50 and the cap layer 40, and stop onthe second dielectric layer 50 to expose the top surface of the trench,the portion surface of the second dielectric layer 50 and the portionsurface of the cap layer 40. The material of the second dielectric layer50 with higher dielectric constant is made of tantalum pentoxide (Ta₂O₅)or aluminum oxide (Al₂O₃). Thus, the higher dielectric constant of thedielectric layer has higher coupling efficiency to improve thecapacitance density of the capacitor structure.

Please refer to FIG. 5. A photoresist layer with a contact windowpattern (not shown) is formed over the substrate 10. An etching processis performed to remove the portion of the second dielectric layer 50 andthe portion of the cap layer 40 to form a first contact window 72 and asecond contact window 74 within the second dielectric layer 50 and thecap layer 40. The first contact window 72 is formed on the first metallayer 222 and to expose the portion surface of the first metal layer222, and the second contact window 74 is formed on the second metallayer 262 and to expose the portion surface of the second metal layer262. In this embodiment, the first contact window 72 and/or the secondcontact window 74 is a single damascene structure or a dual damascenestructure.

Then, please refer to FIG. 6, a metal layer for example Copper (Cu) isformed in the first contact window 72 and the second contact window 74to form a first conductive connecting structure 721 and a secondconductive connecting structure 741 respectively. Then, a planarizationprocess such as CMP process is performed to remove the unnecessary metallayer to form a planar surface on the top of the metal layer. In thisstructure, one end of the first conductive connecting structure 721 iselectrically connected with the first metal layer 222, and one end ofthe second conductive connecting structure 741 is electrically connectedwith the second metal layer 262 to accomplish the embedded capacitorstructure.

According to abovementioned, the advantage is that the embeddedcapacitor structure is formed in the trench, such that the spacestructure for the chip can be reduced to increase the capacitance of thecapacitor structure.

According to abovementioned, another advantage is that the method forforming the embedded capacitor structure only needs one depositionprocess of silicon nitride (SiN) to define the pattern of the embeddedcapacitor structure, such that the deposition processes of the siliconnitride can be reduced during the formation of the embedded capacitorstructure. In addition, the forming processes of the embedded capacitorstructure can compatible with the current manufacturing technology, sothe process can be simplified and the cost can be reduced. In addition,the exposed region of the metal layer (the first metal layer or thesecond metal layer) is enough to allow the formation and alignment ofthe contact window thereon, thus the misalignment issue between thecontact window and the metal layer can be reduced and the incompletestructure of the embedded capacitor would not be formed.

While the invention has been described in terms of what is presentlyconsidered to be the most practical and preferred embodiments, it is tobe understood that the invention needs not be limited to the disclosedembodiment. On the contrary, it is intended to cover variousmodifications and similar arrangements included within the spirit andscope of the appended claims which are to be accorded with the broadestinterpretation so as to encompass all such modifications and similarstructures.

1. A method for forming an embedded capacitor, comprising steps of:providing a first dielectric layer having a trench therein on asubstrate; forming a capacitor structure on a bottom surface of thetrench, the capacitor structure comprises a first metal layer, acapacitance-insulating layer and a second metal layer, and the portionsurface of the first metal layer on the bottom surface in the trench isexposed; forming a cap layer on a top surface and an inner surface ofthe trench, and on the capacitor structure; forming a second dielectriclayer on the cap layer; and removing the portion of second dielectriclayer and the portion of cap layer to form a plurality of contactwindows, the portion surface of the first metal layer and the portionsurface of second metal layer are exposed by the plurality of contactwindows.
 2. The method according to claim 1, wherein the material of thefirst dielectric layer is made of silicon dioxide (SiO₂) or FluorinatedSilica Glass (FSG).
 3. The method according to claim 1, wherein theforming capacitor structure comprising: forming the first metal layer onthe top surface, the inner surface and the bottom surface of the trench;forming the capacitance-insulating layer on a surface of the first metallayer; forming the second metal layer on a surface of thecapacitance-insulating layer; forming a bottom anti-reflection coatinglayer on a surface of the second metal layer and to fill with thetrench; forming a photoresist layer with a capacitor structure patternover the bottom anti-reflection coating layer; etching to remove thebottom anti-reflection coating layer, the portion of second metal layer,the portion of capacitance-insulating layer and the portion of firstmetal layer to form the capacitor structure on the bottom surface of thetrench, and to expose the portion surface of the first metal layer andthe portion surface of the second metal layer on the bottom surface. 4.The method according to claim 3, wherein the material of the bottomanti-reflection coating layer is made of silicon nitride (SiN), silicondioxide (SiO₂) or silicon oxynitride (SiON).
 5. The method according toclaim 1, wherein the first metal layer on the bottom surface of thetrench contacted with the portion inner surface of the trench.
 6. Themethod according to claim 1, wherein the first metal layer with athickness is in a range around 1000 angstroms.
 7. The method accordingto claim 1, wherein the capacitance-insulating layer with a thickness isin a range from 300 angstroms to 600 angstroms.
 8. The method accordingto claim 1, wherein the second metal layer with a thickness is in arange from 600 angstroms to 1000 angstroms.
 9. The method according toclaim 1, wherein the cap layer with a thickness is in a range from 350angstroms to 700 angstroms.
 10. The method according to claim 1, whereinthe contact windows is a single damascene structure or a dual damascenestructure.
 11. The method according to claim 1, further comprising thestep of forming a metal layer in the plurality of contact windows toform a plurality of conductive connecting structures.
 12. An embeddedcapacitor structure, comprising: a substrate having a first dielectriclayer thereon and a trench in the first dielectric layer; a capacitorstructure formed on a bottom surface of the trench, the capacitorstructure comprises a first metal layer on the bottom surface of thetrench, a capacitance-insulating layer on the first metal layer and asecond metal layer on the capacitance-insulating layer, thecapacitance-insulating layer and the second metal layer exposed theportion surface of the first metal layer and there is a distance betweenthe inner surface of the trench and the capacitance-insulating layer andthe second metal layer; a cap layer formed on the inner surface of thetrench and covered on the capacitor structure; a second dielectric layerformed on the cap layer; and a plurality of conductive connectingstructure formed within the second dielectric layer and the cap layer,wherein the portion of the conductive connecting structures iselectrically connected with the portion exposed surface of the firstmetal layer and another portion of the plurality of conductiveconnecting structures is electrically connected with the portion exposedsurface of the second metal layer.
 13. The embedded capacitor structureaccording to claim 12, wherein the material of first dielectric layer ismade of silicon dioxide or Fluorinated Silica Glass (FSG).
 14. Theembedded capacitor structure according to claim 12, wherein the portionexposed surface of the first metal layer is adjacent one side or twosides of the inner surface of the trench.
 15. The embedded capacitorstructure according to claim 12, wherein the distance between the innersurface of the trench and the capacitance-insulating layer and thesecond metal layer is in range from 0.9 um to 1 um.
 16. The embeddedcapacitor structure according to claim 12, the material of thecapacitance-insulating layer is made of silicon dioxide (SiO₂), siliconnitride (SiN), tantalum pentoxide (Ta₂O₅), aluminum oxide or otherinsulating material.
 17. The embedded capacitor structure according toclaim 12, wherein material of the cap layer is made of silicon nitride(SiN) or silicon carbide (SiC).
 18. The embedded capacitor structureaccording to claim 12, wherein the material of second dielectric layeris tantalum pentoxide (Ta₂O₅) or aluminum oxide (Al₂O₃).
 19. Theembedded capacitor structure according to claim 12, wherein theconductive connecting structure is a single damascene structure or adual damascene structure.